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課程名稱 |
交換電路與邏輯設計
SWITCHING CIRCUIT AND LOGIC DESIGN |
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開課學期 |
96-1 |
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授課對象 |
積體電路設計第二專長學程 |
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授課教師 |
李君浩 |
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課號 |
EE2012 |
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課程識別碼 |
901 32300 |
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班次 |
01 |
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學分 |
3 |
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全/半年 |
半年 |
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必/選修 |
必修 |
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上課時間 |
星期四6(13:20~14:10)星期五7,8(14:20~16:20) |
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上課地點 |
明達231明達231 |
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備註 |
本系優先
總人數上限：70人 |
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Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/961logic |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
Ch 1 Introduction: Number Systems and Conversion
Ch 2 Boolean Algebra
Ch 2 Boolean Algebra
Ch 3 Boolean Algebra (cont’d)
Ch 4 Application of Boolean Algebra
Ch 5 Karnaugh Maps
Ch 7 Multi-Level Gate Circuits; NAND NOR Gates
Ch 8 Combinational Ckt Design (skip 8.1, 8.2)
Ch 9 Multiplexers Decoders and PLD (skip 9.7)
Verilog: Combinational Circuits (TA)
Ch 11 Latches and FF
Ch 12 Registers and Counters
Ch 13 Analysis of Clock Sequential Ckts
Ch 14 Derivation of State Graphs and Tables
( Skip examples 2 and 3 in Sec. 14.3)
Ch 15 Reduction of State Tables (skip 15.7, 15.8, 15.9)
Ch 16 Sequential Ckt Design (16.1 to 16.4)
1/3: Additional design problems
1/4: Ch 18 Ckts for Arithmetic Operations (18.1, 18.2)
Supplementary materials |
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課程目標 |
Learn basic theory of switching circuit, basic logic design skills and how to aplly it. |
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課程要求 |
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預期每週課後學習時數 |
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Office Hours |
每週四 16:00~18:00 |
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指定閱讀 |
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參考書目 |
Textbook: C. H. Roth, Jr., Fundamentals of Logic Design,
5th edition, Thomson, 2004. |
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評量方式
(僅供參考) |
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No. |
項目 |
百分比 |
說明 |
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1. |
期中考 |
35% |
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2. |
期末考 |
35% |
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3. |
隨堂測驗 |
11% |
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4. |
作業 |
17% |
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5. |
Participation |
2% |
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週次 |
日期 |
單元主題 |
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第1週 |
9/20,9/21 |
Ch 1 Introduction: Number Systems and ConversionCh 2 Boolean Algebra |
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第2週 |
9/27,9/28 |
Ch 2 Boolean AlgebraCh 3 Boolean Algebra (cont’d) |
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第3週 |
10/04,10/05 |
Ch 4 Application of Boolean Algebra |
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第4週 |
10/11,10/12 |
Ch 5 Karnaugh Maps |
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第5週 |
10/18,10/19 |
Quiz 1
Ch 7 Multi-Level Gate Circuits; NAND NOR Gates |
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第6週 |
10/25,10/26 |
Ch 8 Combinational Ckt Design (skip 8.1, 8.2) |
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第7週 |
11/01,11/02 |
Ch 9 Multiplexers Decoders and PLD (skip 9.7) |
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第8週 |
11/08,11/09 |
11/8 review session (TA)
11/9 Midterm |
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第9週 |
11/15,11/16 |
11/15 停課
Verilog: Combinational Circuits (TA) |
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第10週 |
11/22,11/23 |
Ch 11 Latches and FF |
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第11週 |
11/29,11/30 |
Ch 12 Registers and Counters |
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第12週 |
12/06,12/07 |
Ch 13 Analysis of Clock Sequential Ckts |
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第13週 |
12/13,12/14 |
Ch 14 Derivation of State Graphs and Tables
( Skip examples 2 and 3 in Sec. 14.3) |
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第14週 |
12/20,12/21 |
Ch 15 Reduction of State Tables (skip 15.7, 15.8, 15.9) |
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第15週 |
12/27,12/28 |
Quiz 2
Ch 16 Sequential Ckt Design (16.1 to 16.4) |
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第16週 |
1/03,1/04 |
1/3: Additional design problems
1/4: Ch 18 Ckts for Arithmetic Operations (18.1, 18.2) |
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第17週 |
1/10,1/11 |
Supplementary materials |
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